Sreenivas Reddy Basireddy

#100DaysofRTL Day-93 go to Repetition Operator in SVA Hello all, In SystemVerilog Assertions (SVA), the repetition operators are used to specify how many times a sequence or condition should occur. These operators are essential for describing patterns of behavior that need to be verified over multiple clock cycles. There are several types of repetition operators, each with its own syntax and use case. Goto Repetition ([->]): Specifies that a sequence must occur after a specified number of cycles, with no constraints on what happens in the intervening cycles. Syntax: sequence [->N] where N is the number of clock cycles before the sequence occurs. The goto repetition operator [->] in SVA is a powerful tool for specifying exact timing relationships between events, making it invaluable in verifying timing-sensitive hardware designs. 👉 check my github repo for the verilog code: https://lnkd.in/gd7UNcFC 👉 Hope you learnt something today #100daysofrtl #intel #verilog #linux #texasinstruments #rtldesign #synopsys #cisco #amd #digital #github #githubactions #github #communication #verilog #systemverilog #verification #intel #synopsys #cadence #nxp #mavensilicon #design #qualcomm #verificationengineer #amd #arm #pentium #vlsi #100codesofrtl #systemverilog #verilogcoding #verilog #rtldesign #designverification #intel #education #passionate #vlsi #vlsipassion #brandambassador #coding #rtlcoding #uvm #vlsidesign #perl #pythonprogramming #100codes #codingchallenge #alsemi #agnisys #greensemi #intel #jntu #studentslife #data #like #start #verificationacademy

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Hello LinkedIn Family In 100 days 200 analog layout interview questions series... Day 8..... Q16. why polysilicon used for gate in mosfet rather than metal ..? Ans.... 👇👇 👇 Polysilicon is preferred for MOSFET gates over metal due to its ability to support "self-aligned gate processes", which minimizes alignment issues and parasitic capacitance. Additionally, polysilicon can be heavily doped to achieve desired electrical properties, enhancing device performance and stability at high temperatures. #100DaysChallenge #InterviewPreparation #CareerDevelopment #JobInterviews #InterviewTips #ProfessionalGrowth #LearningJourney #SuccessMindset #CareerAdvice #SkillBuilding #Networking #PersonalDevelopment #JobSearch #InterviewQuestions #CareerSuccess #ContinuousLearning #MentorshipMatters #Inspiration #LeadershipDevelopment #KnowledgeSharing #GrowthMindset #ProfessionalNetworking #InterviewSkills #CareerGoals #SelfImprovement #Empowerment #JobReady #FutureLeaders #Resilience #ConfidenceBuilding

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Good opportunity

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Dear Chip Designers, . . . In the fast faced Semiconductor Industry, A Strong Individuals can Resolve Perceived Weaknesses in Teams. A New hire team lead can make or break the entire team, I have seen this multiple times. In the dynamic landscape of the Semiconductor industry, success often hinges on the collective strength of teams. However, even the most skilled teams may face challenges when dealing with perceived weaknesses among members. In this, lets delve into the transformative power of strong individuals in resolving these issues, ultimately fostering a culture of collaboration, innovation, and success. Identifying Perceived Weaknesses: Before delving into solutions, it's crucial to identify the perceived weaknesses that may hinder team performance. These can range from lack of technical proficiency to communication barriers or even interpersonal conflicts. The Role of Strong Individuals: Strong individuals possess a unique set of qualities that can significantly impact team dynamics. These individuals are not only technically proficient but also exhibit strong leadership, communication, and problem-solving skills. Their presence within teams can serve as a catalyst for positive change, bridging gaps and inspiring others to elevate their performance. Key Solutions and Strategies: Lead by Example: Strong individuals lead not only through their words but also through their actions. By setting high standards and demonstrating commitment to excellence, they inspire others to follow suit. Facilitate Open Communication: Effective communication is the cornerstone of successful teams. Strong individuals actively foster an environment where team members feel comfortable expressing their ideas, concerns, and feedback. Offer Mentorship and Support: Strong individuals recognize the importance of nurturing talent within the team. They willingly share their knowledge and experiences, empowering others to grow and develop their skills. Address Conflict Constructively: Conflict is inevitable within any team, but strong individuals approach it as an opportunity for growth rather than a hindrance. They facilitate constructive discussions and work towards finding mutually beneficial solutions. Celebrate Diversity: Strong individuals appreciate the value of diversity in perspectives and backgrounds. They actively seek out input from all team members, recognizing that innovation thrives in an inclusive environment. Case Studies and Success Stories: To illustrate the effectiveness of leveraging strong individuals within teams, we present real-life case studies from leading semiconductor companies. These stories highlight how the presence of strong individuals has transformed teams, overcoming challenges and achieving remarkable results. As we move forward, let us recognize and empower these individuals to drive positive change and propel our industry towards new heights. #semiconductor #Semiconductors #Chip #VLSI

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Advanced High-performance Bus (AHB) is a part of AMBA bus which is used as a communication and Interface protocol in Subsystem / IP / SOC based design and is essential for both RTL and ASIC Verification in VLSI. Below are the important concepts that are needed to learn AHB protocol. [1] Role of Arbiter and Decoder in AMBA AHB. [2] Different arbitration mechanism in AHB. (Ex: Round Robin, Priority access, etc) [3] Multi Master - Slave interconnection scheme in AHB. [4] Difference between Incrementing and Wrapping Burst. [5] What is an address and data phase in AHB. Why data phase can accomodate multiple cycle. Waveform for Basic transfer operation. [6] Total maximum No. Of wait states can be inserted as a delay in AHB cycles. [7] Difference between Sequential and Non-seqiential transfer. Role of Idle cycle. [8] What is the role of default Slave and when it is needed. [9] How the address decoding operation execute in AHB. [10] Early Burst termination mechanism. [11] What are the different response mechanism scheme in AHB. Role of HreadyIn and HreadyOut signal. [12] What is the difference between Split and Retry operation. Why OK response execute in single cycle and Error, Retry and Split need at least two cycles. [13] How the arbiter decide which Master to grant access to the bus. Role of HGRANTx and HBUSREQx signal. [14] Role of default master and why it only execute Idle cycle. [15] Locked transfer operation in AHB. [16] How to prevent deadlock when multiple master try to access the bus. How AHB handles multiple split transfer. [17] Operation of AHB bridge in AHB to APB interface. [18] Limit of boundary access in AHB. What will happen if the slave try to access out of bound address range. [19] No. of channels in AHB and it's pipelined architecture. [20] What is the role of dummy master in AHB. #vlsi #asic #semiconductorindustry #electricalengineering

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Class B amplifiers are sometimes OK for RF but not audio. Why? 👇🏽 Class B amplifiers provide a highly distorted output signal, but with good amplification efficiency. For many RF applications, it is okay to distort the carrier signal as long as the modulation is not affected. The baseband information can still be retrieved. Class B won't work for audio. It is a complex time-varying signal which needs to be accurately amplified. To still get Class B efficiencies, the push-pull amplifier was invented. It is a differential version of a Class B amplifier that can produce amplification with good efficiency. If you'd like to learn more about Class B and push-pull amplifiers, stay tuned for this week's newsletter. ✍🏼 Sign up here: www.viksnewsletter.com What is your experience with Class B or audio? Let me know! ~~ 🔔 Follow me for posts on RF engineering ♻️ Repost if you found it useful.

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Hello Linkedin Family I am starting a series.... 100 days 200 analog layout interview questions for a fresher.... I Hope these questions help many freshers... 1) what is the sub threshold Voltage in MOSFET......? Answer.....👇👇👇 Subthreshold voltage in a MOSFET refers to the gate-source voltage (VGS) that is slightly below the threshold voltage (VT), typically around 50 mV less than VT. In this region, the device exhibits exponential current behavior rather than the quadratic relationship seen in saturation, allowing for lower power consumption and improved performance in digital applications #mosfet #vlsi #vlsifreshers #freshers #analoglayout #questuins

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Mirafra Software Technology Hiring Multimedia Framework/Device Driver Leads for Hyderabad location !!! Requirement 1- Android/Linux audio lead Job Description: ● Deep understanding of the Android audio architecture, including Audio Flinger, Audio Policy Service, and Audio Track/Audio Record classes. ● Familiarity with how the Android audio framework interacts with the underlying hardware through the Audio Hardware Abstraction Layer (HAL). ● In-depth knowledge of audio frameworks such as ALSA and PulseAudio for Linux. ● Experience with Android’s audio HAL (Hardware Abstraction Layer) and AudioFlinger. ● Understanding of the Android Audio Manager and MediaCodec. ● Knowledge of standard audio protocols (e.g., I2S, SPDIF, HDMI audio). ● Understanding of audio codecs and formats (e.g., PCM, MP3, AAC). ● Expertise in developing and maintaining audio device drivers. ● Familiarity with driver frameworks and APIs used for audio hardware integration. Requirement 2 - Android/Linux camera/video lead Job Description: ● Experience working with full camera software stack - application, camera services, HAL, Camera kernel and drivers ● Understanding of Linux camera frameworks such as V4L2 (Video4Linux2) and how they manage camera hardware and video capture. ● Familiarity with the Android camera framework, including Camera HAL (Hardware Abstraction Layer), CameraService, and CameraManager. ● Expertise in developing and customizing the Camera HAL to interface between the Android camera framework and camera hardware. ● Knowledge of HAL interfaces, including how to implement and extend HAL functions for different camera modules. ● Understanding of image processing algorithms and how they are applied in the camera pipeline, such as auto-focus, white balance, and exposure control. ● Camera sensor driver development and integration into Linux/Android ecosystem Requirement 3 - Android/Linux display/graphics lead Job Description: ● In-depth knowledge of Android’s display stack, including Surface Flinger, Hardware Composer (HWC), and the various layers involved in rendering and compositing ● Deep understand of display hardware accelerator and graphics hardware rendering pipeline and respective software flows ● Experience with Android’s display manager and handling different display modes, resolutions, and refresh rates ● Experience with developing or customizing display drivers (LCD, MIPI, HDMI, LVDS) including integration with Android’s display HAL (Hardware Abstraction Layer). ● Proficiency in graphics APIs such as OpenGL ES, Vulkan, ● Experience with Linux kernel internals and writing kernel modules related to display and graphics. ● Experience with performance profiling tools and techniques for identifying and resolving graphics/display issues. Exp-10-15 years Location: Hyderabad Notice Period: Immediate Interested can share relevant resume to maheshvastrad@mirafra.com

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How to start verifying a simple RTL design (Ex. Memory Controller) in UVM --> 1st Part: The very step is to understand the specification thoroughly with each of the below details: a. Working principle b. I/O ports and Signal level description c. Submodule details d. Is there any dependency of one signal with another, etc. e. Design detail understanding The next step is to build the Verification Plan and Feature / Testcase plan. List down the features that are needed to be verified. Some of them are below: ✓ Check whether clock and reset are working correctly. ✓ Check the correctness of the data by writing some value and read the same value of a single register. ✓ Repeat the process for all register. ✓ Check the default value of the register by reading the data. ✓ Check the controllers ability to handle multiple write and read transaction and Back to back writes. ✓ Check the correctness of WO register by reading from them. ✓ Check the correctness of RO register by writing on them. ✓ Check the Address translation and Address decoding issues being handled correctly. ✓ Check the invalid address access by RW from invalid or out of range addresses. ✓ Check the accessibility of locked condition of register. ✓ Check the controllers capability of accessing a single register from multiple address of different submap. ✓ Check the enablement and Quircky register accessibility. Above is a indicative list. Apart from the one mentioned above one also needs to add below cases: a. Stress testing. b. Use callbacks to inject errors. c. Multiple regression. d. Corner cases. The next step in order to verify the features verification planning is needed for which we need to code the following UVC's / objects along with Interface. a. Transaction b. Driver c. Monitor d. Sequencer e. Agent f. Sequence item g. Configuration h. Env i. Test #vlsi #asic #electronics #engineering

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#Micron, #Hyderbad is looking #Mtech Freshers from Premium colleges. and Good exposure on #Python #semiconductor Knowledge #EDA Tools #Verilog #CMOS #UART #TCAD Share your Updated CV to ggrandhivenk@micron.com Connect with Our Hiring Team: Narayanan Ramanan Gopi Krishna Vemuri Rajesh Kumar Gupta Seema Kharayat Shrashti Sai . Revathi P #Mtech #Freshers #IIT #NIT #Mirconhiring #Hyderbad #Python #Scripting

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Just a thought RTL Design has few logics which is not required as per the design specifications, this portion of code gets excluded in code coverage analysis. By knowing this fact we still synthesis the logic and it increases the gate counts. but functionaly this logic has no use. Now can this be a area for AI based tool to discard that portion of logic during synthesis and we reduce the gate count?

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One needs to be completely aware of the communication protocol as a Verification or RTL Engineer since it's been used on a multiple interfaces. The first popular set of Protocols are from AMBA family which comprises of APB, AHB, AXI, ATB, ACE, etc. ☆APB is a part of AMBA bus which is basically used for low power peripherals like Uart, timer, etc.Besides this Register programming can also be done using APB through RAL depending on the type of adapter being used. ☆Another important protocol which is a part of AMBA bus is AHB (Advance High Performance Bus) which is used for High Frequency Synthesizable Design and it supports multiple Bus Master, Burst transfer, Split transfer (in AHB5 it's not there) and pipelined operation. ☆AXI is another important interface protocol of AMBA as it supports multiple channels, outstanding and out of order transaction. ******* Note **** [1] There are differences b/w AXI3 and AXI4 as the write data interleaved, locked access are removed in AXI4 and AXI4 support QOS, A*region, A*physical signalling scheme. [2] There are differences in AHB and AHB5 as well since retry and split are not present in AHB5 and it support more feature similar to AXI. **************** ☆ATB is an useful protocol which is useful in trace debug coresight. Now coming to communication protocol you should have throrough knowledge of these two protocols: ✓ I2C(Inter Integrated Circuit) ✓ SPI(Serial Peripheral Interface) Both of them are serial communication protocol and are most basic ones. Regarding I2C, someone needs to be aware of the following concepts: a. Arbitration and Clock stretching b. Clock Synchronisation c. Concept of SDA and SCL lines. d. Addressing modes, Start and Stop bits. e. Master and Slave Configuration ✓ Apart from the above one should have a good understanding about Synchronous and Asynchronous FIFO. Some of the important Asynchronous FIFO concepts are: a. FIFO Depth Calculation. b. FIFO full and empty condition. c. Difference between Binary and Gray Pointer. d. Almost full and empty condition. e. Verilog code of Async Fifo. f. Different ways of implementing Async Fifo. #vlsi #asic #semiconductorindustry #electricalengineering

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To start verifying the chip in VLSI is a critical task because before that there are series of steps and methodical approach that needs to be followed like verification planning, Test plan creation, Feature extraction, Assertion plan, etc. Below are the brief list of some of the tasks in a systematic manner which are useful for ASIC Verification. [1] To understand the Design Specification and its functionality, involved in Feature Extraction, identify the Test Scenarios, I/O Port List. [2] Identify the different constraints related to clock, timing, delay and power and also define the scope of verification with all the metrics. [3] Ensure the DV guidelines like documentation, regression suite maintenance, bug tracking, coding guidelines, review with designers, etc are followed by everyone. [4] Prepare the Verification Plan which will involve all the metrics of the Verification like the Testbench Architecture, UVC Description, Reference Model, Checkers and the Verification Flow. [5] Prepare the TestPlan, identify the Directed and Corner case scenario. The Plan can be subdivided into Functional Test Cases, Connectivity Checks, Data and Control Path Checks, Register Testing, etc. [6] Start Coding the UVC's and when a basic Testbench Infrastructure is ready, verify it with a Sanity TestCase. [7] Code the Scoreboard and there are multiple ways to do it either with tlm analysis fifo, set of queues and arrays, imp macros, etc. Depending on the need there might be a requirement to design an inorder or out of order comparator and it will check the integrity of TB. [8] Use the Configuration wisely and start with coding more Test Scenario extending from Base Test or a library of Sequences. [9] Prepare a Bug Rate Chart and usually at the initial level Bugs can be caught with the Directed Testcase. But once the Bugs start dropping it's the time to introduce Corner Cases, Functional Coverage and Assertions. [10] Start Preparing a Assertion plan and initiate Functional and Code Coverage. Code Coverage will let you know how much Code has been exercised and Functional Coverage will deal with the Functionality. [11] Launch the Assertion and monitor the report. [12] Launch Formal Verification such as RTL2RTL checks, model checking, LEC, CDC analysis to catch more issues within the design. [13] Identify the coverage Holes and write more Testcases to cover the loopholes. Implement Checkers which are inbuilt in Assertions and it will help more in Verification. [14] When the Coverage goal achieved, launch the GLS (Gate Level Simulation) which is generated over the netlist. [15] To check the Power Aware Verification enabling the UPF based flow. [16] Maintain the regression test suite and keeps running the test for multiple iteration to reduce the probability of occurance of any bugs to zero. The above steps might vary while doing IP, SOC or a subsystem verification. #vlsi #asic #electronics #engineering

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Question of the day 1)What is the boot sequence flow in soc? #vlsi #verilog #uvm #trend #dv #dfx #dfd #pd #ai #ml #ovm #sv #systemverilog #freshers #semiconductor

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Unlock Your Potential: 10 Tips to Grow as a VLSI Engineer As a VLSI Engineer, you're part of a highly specialized field that's driving technological innovation. To stay ahead, continuous learning and growth are crucial. Here are 10 tips to help you advance your career: 1. Stay Current with Industry Trends Follow industry leaders, researchers, and publications to stay updated on: - Emerging technologies (AI, IoT, 5G) - New design methodologies (FinFET, 3D IC) - Advancements in EDA tools (Synopsys, Cadence) 2. Develop a Strong Foundation in Digital Design Master: - Verilog/VHDL - Digital logic design - Microarchitecture - FPGA design 3. Expand Your Skill Set to Analog and Mixed-Signal Design Learn: - Analog circuit design - Mixed-signal design - ASIC design - Physical design 4. Familiarize Yourself with EDA Tools Proficiently use: - Synopsys (VCS, Design Compiler) - Cadence (Innovus, Virtuoso) - Mentor Graphics (ModelSim, Questa) 5. Participate in Projects and Competitions Join: - VLSI design contests - Hackathons - Open-source projects - Research initiatives 6. Network with Peers and Industry Experts Attend: - Conferences (DAC, ICCAD) - Workshops - Webinars - Online forums (Reddit, LinkedIn groups) 7. Pursue Higher Education and Certifications Consider: - Master's or Ph.D. in VLSI or related fields - Certifications (VLSI Design, ASIC Design) 8. Stay Up-to-Date with Industry Standards Familiarize yourself with: - IEEE standards (1801, 1076) - IPC standards (J-STD-020) 9. Develop Soft Skills Improve: - Communication - Teamwork - Time management - Leadership 10. Join Online Communities and Forums Engage with: - VLSI subreddit - VLSI professionals on LinkedIn - Online forums (EDABoard, VLSI Forum) Take Your Career to the Next Level! By following these tips, you'll enhance your skills, stay industry-relevant, and advance your VLSI engineering career. Share Your Thoughts! #VLSI #Semiconductor #Engineering #CareerDevelopment #IndustryTrends #Innovation #Technology Bala Gorthi Rekha P Jyothi G Rushang shah Eximietas Design BinduLatha D

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Lets discuss on Coverage: 1)It is one of the metric for the verification engineers to signoff any verification project  2) It will measure the tested and untested portion of your design Coverage is of two types: Code coverage -Automatically generated by the tool              Functional coverage -user should define the bins 1)what is missing in Code coverage? Example1: Let say you have a 32-bit register in your desing ,Just by doing (write 32-bit 0's -> write 32-bit 1's -> write 32-bit 0's) you will get 100% code coverage for this register,But functionality was it is working as expected or not Example2: Lets say you have a feature X in your Design specification,But RLT Design engineers missed to write the code for that feature It can't be catch using code coverage,But if you write a bin for that feature you can catch in functional coverage 2)What is the draw backs of functional coverage? Functional coverage is defined by the Verification engineers based on Design specifications Let say they are 10 features in the design ,But some how the engineer overlooked it and written 8 features then there is a chance of missing functionalities 3)If i miss writing functional coverage for one feature and no test case for that feature, So how do you catch this issue? There is a chance to catch this issue in code coverage #VLSI #DV #DFX #PD #UVM #SV #VERILOG #SEMI #AL #ML #AXI #PCIE #UART #DDR #SPI

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Lets discuss on Coverage: 1)It is one of the metric for the verification engineers to signoff any verification project  2) It will measure the tested and untested portion of your design Coverage is of two types: Code coverage -Automatically generated by the tool             Functional coverage -user should define the bins 1)what is missing in Code coverage? Example1: Let say you have a 32-bit register in your design ,Just by doing (write 32-bit 0's -> write 32-bit 1's -> write 32-bit 0's) you will get 100% code coverage for this register,But functionality was it is working as expected or not Example2: Lets say you have a feature X in your Design specification,But RLT Design engineers missed to write the code for that feature It can't be catch using code coverage,But if you write a bin for that feature you can catch in functional coverage 2)What is the draw backs of functional coverage? Functional coverage is defined by the Verification engineers based on Design specifications Let say they are 10 features in the design ,But some how the engineer overlooked it and written 8 features then there is a chance of missing functionalities 3)If i miss writing functional coverage for one feature and no test case for that feature, So how do you catch this issue? There is a chance to catch this issue in code coverage #uvm #verilog #sv #systemverilog #pd #dv #dfx #amba #axi #protocol #vlsi #semiconductor

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How Artificial Intelligence is going to improve chip design? Artificial intelligence is going to enter in almost every sector wherever job can be automated. VLSI chip design is also going to be benefitted by using AI. Already many companies have started using AI in their tools. Some key points about AI in VLSI AI Applications in VLSI: 1. Design Automation: AI optimizes chip design, reducing manual effort and increasing productivity. 2. Layout Optimization: AI algorithms optimize chip layout for better performance, power consumption, and area utilization. 3. Verification and Validation: AI-powered tools detect bugs and errors, ensuring high-quality chip designs. 4. Manufacturing Yield Prediction: AI predicts manufacturing yield, enabling proactive defect reduction. 5. Test Pattern Generation: AI generates efficient test patterns, reducing testing time and costs. 6. Chip Performance Optimization: AI optimizes chip performance, power consumption, and thermal management. AI Techniques Used: 1. Machine Learning (ML): ML algorithms learn from data to improve design and manufacturing processes. 2. Deep Learning (DL): DL techniques, like neural networks, analyze complex design and manufacturing data. 3. Natural Language Processing (NLP): NLP enables human-AI collaboration and design documentation analysis. 4. Computer Vision: Computer vision techniques inspect and analyze chip designs and manufacturing data. Benefits: 1. Increased Efficiency: AI automates repetitive tasks, freeing engineers for high-value tasks. 2. Improved Quality: AI detects errors and optimizes designs, ensuring high-quality chips. 3. Reduced Time-to-Market: AI accelerates design and manufacturing processes. 4. Cost Savings: AI reduces design and manufacturing costs. Challenges on the way: 1. Data Quality: AI requires high-quality, relevant data for effective learning. 2. Interoperability: Integrating AI tools with existing design and manufacturing systems. 3. Security: Ensuring AI-driven design and manufacturing processes are secure. And more importantly the main thing about adoption of AI is trust on the entire process. what do you think which direction AI would go in chip design? #vlsi #chip #design #Artificial #intelligence

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Very-large-scale integration (VLSI) is the process of creating an integrated circuit (IC) by combining millions or billions of MOS transistors onto a single chip. VLSI began in the 1970s when MOS integrated circuit (Metal Oxide Semiconductor) chips were developed and then widely adopted, enabling complex semiconductor and telecommunications technologies. The microprocessor and memory chips are VLSI devices. Before the introduction of VLSI technology, most ICs had a limited set of functions they could perform. An electronic circuit might consist of a CPU, ROM, RAM and other glue logic. VLSI enables IC designers to add all of these into one chip.The first semiconductor chips held two transistors each. Subsequent advances added more transistors, and as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). Further improvements led to large-scale integration (LSI), #snsdesignthinkers #snsinstitution