Talk:Dual in-line package

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Text and/or other creative content from this version of Dual in-line package was copied or moved into Quad in-line package with this edit on 16:57, 18 December 2021. The former page's history now serves to provide attribution for that content in the latter page, and it must not be deleted as long as the latter page exists.

Dual in-line package and Dual-Inline Package should be merged. --Anonymous

Agree. BTW it's generally good to sign and date posts to talk pages. There's been some discussion on the village pump as to the proper name for the merged article. Andrewa 03:57, 27 Oct 2004 (UTC)

I took the chance of establishing the present article as the merged one. My sources indicate that this title is the correct and most used one. I guess potentially disagreeing contributors will let themselves be heard. --Wernher 18:49, 27 Oct 2004 (UTC)

Agree, see Wikipedia:Village pump (miscellaneous)#DIP^{(link fixed by plugwash)}. Andrewa 01:10, 28 Oct 2004 (UTC)

May I know what is the highest pin count a dual in line package can go now?

The largest common size is 40 pin but bigger sizes have been used by some chips in the past (for example the megadrive CPU). I don't know exactly how big the largest one ever produced was though.

its like comparing e-mail with morse code! Plugwash 09:38, 2 April 2006 (UTC)[reply]

don't PDips have 0.05" spacing?::

Jkoether 10-13-06

All the dips i've ever seen (whether plastic or ceramic) had a .1 inch spacing between two pins in the same row. Most have a .3 or .6 inch spacing between the rows but I have seen other widths particularlly with sensor chips. SOIC (the surface mount package which took over from dip) has a 0.05 inch spacing. Plugwash (talk) 01:33, 17 May 2008 (UTC)[reply]

The intel reference given by ISBN *may* be the same as http://www.intel.com/design/packtech/packbook.htm , but I'm reticent to add it to the references section, since I have no indication that anything in the article was written based on it. In purticular, several sections of chapter 2 give you various sorts of DIP (sadly, only in certian pin-counts, they don't give a general formula for the parameters, nor does it give the size I'm looking for).

I think there needs to be a chip connection categorisation system on Wikipedia, maybe to be expanded to other components. So lets say I was looking for Dips, I should be able to go to chip_packaging (or some such name) an then it'll have a list. Split the list up by things like: Surface mount, solder in, square, rectangular, PGA, BGA ....

What do you think?

--Stripy42 (talk) 15:58, 15 January 2008 (UTC)[reply]

Absolutely! Although actually, I came here while trying to find something on S08... no index for footprints either. —Preceding unsigned comment added by 150.101.166.15 (talk) 06:03, 15 May 2008 (UTC)[reply]

SO8 probablly means 8 pin SOIC Plugwash (talk) 02:01, 17 May 2008 (UTC)[reply]

Bemused to see that the common understanding from the 70s and 80s, when these packages where common, doesn't even rate a mention. A DIPP was a Dual Inline Pin Package. A DIP-8 package was a Dual Inline Pin package with 8 pins. Not that I have a web page from the '70s to refer to, but it's interesting to see history slip away like that.150.101.166.15 (talk) 06:41, 15 May 2008 (UTC)[reply]

The article currently says: Shrink Plastic Dual In-line Package (SPDIP) – A shrink version of the PDIP with a 0.07 in (1.778 mm) lead pitch

I'm not sure this is always true.

This document:

http://ww1.microchip.com/downloads/en/DeviceDoc/39632D.pdf

Section 30.2 (PDF page 405, indicated page 403) says it's an SPDIP, but shows the pitch (dimension "e") at 0.100 inches.

I'm just a programmer, so I can't say for sure. Any wisdom from you hardware guys? —Preceding unsigned comment added by 68.62.236.143 (talk) 02:31, 12 August 2008 (UTC)[reply]

The problem is the terminology is confusing, "shrink dip" is a term for DIP packages with a narrower than usual pin spacing. "Skinny dip" reffers to dip packages of the narrower .3 inch rows spacing (especially ones with pin counts traditionally associated with the wider 0.6 inch row spacing). Of course both shrink and skinny can be abriviated with an s.

I searched for 'SDIP' and came up with nothing, maybe it should be redirected here. Also, the relevant section doesn't mention this abbreviation, though it is fairly common. This is especially important as it is hard to find out what this abbreviation represents otherwise; many abbreviation sites fail to list it, and "define: SDIP" in google also fails. --CMH —Preceding unsigned comment added by 83.100.202.7 (talk) 19:49, 10 June 2009 (UTC)[reply]

'SDIP' = "Skinny DIP" referrring to DIPs that are 0.3 inches wide. SDIP is used in Microchip Data Sheets for packaging descriptions. It may not be an industry adopted acronym. (ajs Dec 13, 2009 20:36 (EST)) —Preceding unsigned comment added by 69.137.232.203 (talk)

I've personally used machine-pin headers to make PGA sockets, and these headers are also compatible with DIPs. Therefore, to say that a DIP socket is incompatible with PGAs is incorrect. Perhaps the conventionally available ones are, but I can still construct a socket that fits both. Because most sockets won't fit a PGA (only the ones without support structures in the way of the pins), I've changed it to "rarely true". If the intended message pertains only to store-bought complete sockets, rather than home-made variants, go ahead and change it back.

118.208.188.64 (talk) 13:54, 29 October 2010 (UTC)[reply]

I haven't seen a lot of pick and place machines, but the ones I have seen, can't see the parts they insert. How does the machine know if the notch is there, or if it's a dot or indent in the package? --Wtshymanski (talk) 14:46, 6 October 2011 (UTC)[reply]

There's SIP for single rows, DIP for double rows, QIP for quad rows. So you'd think triple rows would be called TIP, but from what i'm seeing around they're just called DIP still, urgh so confusing! Roidroid (talk) 03:39, 2 November 2013 (UTC)[reply]

The article says:

Intel and 3M developed the quadruple in-line package (QIP or QUIP), introduced in 1979, to boost microprocessor density and economy.

However, while it is referenced, Rockwell Semiconductor has been manufacturing the Rockwell PPS-4 (datasheet) using 42-pin QIP packaging since 1972.

--CyberXRef^talk 13:44, 10 January 2014 (UTC)[reply]

While a counterclockwise numbering notation is widely used for DIP's..... There are clockwise numbering notations and that usually indicates that the die is mounted "cavity down" (the die is on the bottom side of the package) rather than the usual cavity up. I have no references but I think it'd be easy enough to research and add a little more info to this section. 12.41.140.254 (talk) 15:46, 22 August 2014 (UTC)[reply]

Fascinating - but is it in a book somewhere? --Wtshymanski (talk) 02:13, 24 August 2014 (UTC)[reply]

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I see "typical lead counts are 8, 14, 16, 18, and 28; less common are 4, 6, 20, and 24 lead counts" (and I came from 555 timer IC, interesting to know that it even has more leads than a uC; wander why..). [Could you go down to, 3, 2.., 1?]

I understand this to mean the "legs" or pins; The minimum seems to be shrinking, I recall 8-bit CPUs (and higher) and ROMs etc, with more than 6 pins. That is the lowest pin count I've found for 8-bit microcontrollers now. The lowest I found for 32-bit ARM uC is 8-pin. I noted the Rent rule, and it seems to be about power (only?). All things equal 32-bit CPUs might take more power, but all needs not be equal; This may be the wrong place to ask, is there a reason 32-bit (first ARM [I owned] had many more pins) can't have the same pin count as 8-bit or even 4-, or 1-bit (or 2-bit I found out existed..)? I know about address and data-lines; here I mean with RAM (and maybe cache) and flash, onchip. I'm really thinking of any technology, needs not be DIP..

Bonus question, is there a minimum size you can cut a die into? Is the minimum realistic size, more or less bound by the minimum chip/DIP size, e.g. you need a certain amount of pins and area for each? Has it already been reached? comp.arch (talk) 21:36, 22 November 2016 (UTC)[reply]

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The Construction section first says that plastic DIP (plastic seems implied since it's contrasted to ceramic) is made via a thermoset molding process. The second paragraph says it is done by fusing or cementing the plastic halves around the leads. That sounds like a different process; in the first, all of the housing is viscous and pressed onto the lead-frame-and-die, and in the second, there are two solid halves which are cemented or fused. Either it could do with clarification, or one of the two is wrong. — Preceding unsigned comment added by Digital Brains (talk • contribs) 11:50, 3 June 2019 (UTC)[reply]

The introduction says "Common packages have as few as three [...] leads", whereas Lead count and spacing says "The number of leads is always even." I suspect the three-lead variant has pins missing for greater clearance between pins when the voltages require more clearance than usual. But still, these two sections contradict each other. Digital Brains (talk) 11:57, 3 June 2019 (UTC)[reply]

I'm disappointed to find there is no history in this article. I came here trying to find out when this package was invented. There is some possible material here: [1] GA-RT-22 (talk) 02:42, 13 March 2021 (UTC)[reply]

There is some history in the introduction. Much of the information in the article is old and less relevant today. The article could use some reorganization to distinguish between old uses and current trends. Agnerf (talk) 04:36, 26 May 2021 (UTC)[reply]

There have been speculations for several years about whether DIP packaging is on the way out. [2] More and more ICs are no longer available in DIP packagages. It is difficult to find information about how long chip manufacturers expect to keep producing DIP package versions. A section about this would be relevant for producers of small series products, prototyping, university projects, hobbyists, etc. If anybody can find relevant information about this, please post links here. Agnerf (talk) 04:36, 26 May 2021 (UTC)[reply]