lowRISC / opentitan
OpenTitan: Open source silicon root of trust
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OpenTitan: Open source silicon root of trust
Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
BaseJump STL: A Standard Template Library for SystemVerilog
RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
RISC-V Debug Support for our PULP RISC-V Cores
Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components