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With over 14 years of experience in technical product and program management, I have…

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Experience & Education

  • Bose Corporation

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Licenses & Certifications

Volunteer Experience

Courses

  • Advanced Computer Networks

    CE 6390

  • CCNA

    4.0

  • Computer Architecture

    CE 6304

  • Design and Analysis of Computer Algorithms

    CE 6363

  • Embedded Systems & Wireless Protocols

    TIFAC CORE R&D LAB

  • Machine Learning

    CS 6375

  • Microprocessor Systems

    CE 6302

  • Network Virtualization & Software Defined networking

    -

  • Operating System

    CS 5348

  • Real time Systems

    CE 6308

  • Sensor Network:IoT

    EESC 7v86

  • VLSI DESIGN

    CE 6325

Projects

  • Implement & Validate Cross validation Nearest Neighbor Algorithm(Machine Learning Procedures)

    Implement Nearest Neighbor using Cross validation process and check for efficiency of data partition and estimation parameters. Evaluate it across platforms using Matlab, R , Python libraries and functions. Also develop and implement the procedure in Java

  • Software defined Networking and Virtualization

    Covered diverse perspectives from distributed systems and programming languages, to formal verification and algorithms, identify abstractions that lower the barrier for innovation inside the network with faculty staff.

    See project
  • End to End Internet of Things Solution Platform

    Design and develop all layers of Sensor Mote platform, study and analysis of power efficient protocols like 6LoWPAN, Low power Bluetooth and simulate result for a cloud based IoT system and perform knowledge extraction using machine learning algorithms using Weka tool.

    Other creators
    • shashirekha gundur
    • anjoo saxena
  • ARM Cortex M3 and MSP 430 based software developments for microprocessors

    A general overview of MSP 430 and ARM Cortex M3 Architecture, Instruction Set and Clock Software development in C and Assembly, Polling and Interrupts, Low Power Modes Digital I/O interfaces,(ADCs), Serial Communication (UART, SPI, I2C), Embedded Wi-Fi using Code Composer Studio, JTAG, lab equipment.

    Other creators
    • deepika lakshmanan
  • Research Activity: Low Power and Fault tolerant Memory systems

    - Present

    To study, analyze and stimulate results for STTRAM-DRAM Hybrid memory system.
    Optimize energy consumptions for different processor architectures implementing various algorithms for paging and replacement algorithms.

  • Wireless Interoperability at various IP layers and between different protocols

    Study, analyses and design of packet formats and design, performance trade-off at various layers of IP (like b/w application and transport; transport and network) for RTP and wireless protocols standards in team of 4.
    Simulated a model for mobile adhoc IP network for real time media services and evaluated QoS offered by the design using NS2 tool(python).

    Other creators
  • Analyse processor performance for different cache Implementation

    Simulate to compare the processor performance and memory cache design to optimizing cycles per instructions with various modifications in cache size ,level, associativity and cache block size

  • 2D elastic ball collision

    -

    Optimization of Physics Engine to simulate motion of a ball under gravity and elastic collision with fixed obstacles. Using C language on Texas Instrument's ARM Cortex M4 based Stellaris® microcontroller, motion of a ball under gravity was simulated and the results were shown in real time on a PC. Communication between the microcontroller and the PC was established using UART interface and Java GUI was designed to show the moving balls and their collision in real time on the PC screen.

    See project
  • Design of a control system for an automated rover system

    -

    Team based project to define, code and implement an automatic rover system that handles priority assigned tasks and executes in real time environment (VxWorks) with timing constraints.
    Various methodologies and skills like coding in C, java, handling and communicating with sensors and device drivers (USB, camera) and timing protocols were involved.

    Other creators
  • Optimal cache Design

    Cache design choices (i.e. number of levels, size, associativity, replacement policy etc.) affect the performance of a microprocessor. In this project, we tune the cache hierarchy of an Alpha microprocessor for 4 individual benchmarks.
    The cache design parameters modified were:
    Cache levels: One or two levels, for data and instruction caches.
    Unified caches: Selection of separate vs. unified instruction/data caches. For example, you can have separate L1 caches and a unified L2…

    Cache design choices (i.e. number of levels, size, associativity, replacement policy etc.) affect the performance of a microprocessor. In this project, we tune the cache hierarchy of an Alpha microprocessor for 4 individual benchmarks.
    The cache design parameters modified were:
    Cache levels: One or two levels, for data and instruction caches.
    Unified caches: Selection of separate vs. unified instruction/data caches. For example, you can have separate L1 caches and a unified L2 cache.
    Size: Cache size, one of the most important choices.
    Associativity: Selection of cache associativity (e.g. direct mapped, 2-way set associative, etc.).
    Block size: Block size of the cache, usually 64 or 32 bytes.
    Block replacement policy: Selection between FIFO, LRU and Random

  • Design of Low power, minimum layout area ALU

    -

    Implemented a 16 bit ALU using the IBM 130nm kit; involving architecture design, RTL design, verification, synthesis, optimization, placement and routing, postlayout simulation and testing.
    Gate level synthesis performed using Synopsys tools; Routing performed using Encounter.

  • Cubesat Satellite Design, Indian Space Research Organization

    -

    Designed, built and tested the communication system including Antennas, Transceivers and TNC’s and verify its working after deployment on system with other equipments such as power and microcontroller devices.

  • Controller Area Network

    -

    Developed a circuit that makes high speed and collision free communication between multiple devices or nodes using Freescale HCS-12 board to be deployed on heavy vehicles

Honors & Awards

  • Bravo

    New Devices Group Hardware platform

    This award honors the impact you have demonstrated through Customer Orientation

  • Outstanding Contributor

    Student Success Center, University of Texas at Dallas

    For dedicated and hard working efforts towards the job in Math Lab and Student Services Center.

  • Employee Appreciation

    Design Automation team, IDG

    Token of Appreciation and recognition for effort and contribution towards tool development as an intern assignment.

  • VP FINANCE AIESEC DALLAS

    AISEC DALLAS

    Appointed as Vice President of Finance,AIESEC Dallas and key member exchange team.

  • Contribution to Test and Efficiency Symposium

    Chief technology Officer

    Presented the paper “Testing Multicore Software: The Agile Way” in “Test and Efficiency Symposium” at Austin
    Market research ‘4P’s in 4Months’ based on “time to market” technique of SoC’s was published on Engadget.

  • Certificate of Merit

    TIFAC CORE AUTOMOTIVE ELECTRONICS R&D CENTRE

    Awarded certificate of merit for research work and project carried out during "embedded systems and wireless protocols course" in ADAS and in-vehicle infotainment systems.

  • Certificate of merit

    Indian Space Research Organization

Languages

  • Spanish

    Limited working proficiency

  • German

    Elementary proficiency

  • English

    Native or bilingual proficiency

  • Hindi

    Native or bilingual proficiency

Organizations

  • AIESEC DALLAS

    -

    - Present

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